1. Field of the Invention
The present invention relates to a fabricating method of semiconductor devices, a fabricating method of printed wired boards, and a printed wired board, all of which are suitable in improving wiring efficiency and in realizing easy drawing of circuit pattern, and in particular relates to a fabricating method of semiconductor devices of chip scale package (CSP), a fabricating method of printed wired boards being used for the CSP, and a printed wired board being used for the CSP.
2. Description of the Related Art
In recent years, due to the demand for semiconductor packages of smaller size, chip scale packages (CSP) using a semiconductor chip in the center of which bonding pads are located is attracting attention to realize semiconductors of chip scale size.
FIG. 10 is a cross section showing schematically an example of such semiconductor package of chip scale size.
In this semiconductor device 1, on a semiconductor chip 3 of center-pad structure in which, for instance, two rows of pads 2 are disposed in the center portion thereof, a printed wired board 4 of tape shape is adhered through an adhesive layer 5, a bonding wire 6 is bonded by pressure bonding to a bonding pad of the printed wired board 4 and the pad 2 of the semiconductor chip 3 to connect these electrically, and thereon for instance humid-resistant insulating curing resin 7 such as silicone resin is potted to seal the bonding wire 6. Reference numeral 8 shows solder balls that are mounted on terminals that are concurrently terminals for external input/output and fixing means of the semiconductor device 1.
A printed wired board 4 that is used for the semiconductor package of this semiconductor device 1 is fabricated by the use of the steps shown in, for instance, FIG. 11A, FIG. 11B, FIG. 11C, FIG. 11D and FIG. 11E, and is further supplied to the following step shown in FIG. 11F.
First, copper foil 9 and insulating film 10 such as polyimide are adhered through adhesive (FIG. 11A). The copper foil 9 is etched out leaving only portions necessary as circuit pattern and pads, leads, terminals or the like, resulting in that which is shown by reference numeral 91 in FIG. 11B.
Next, except for the portion necessary of gold plating such as pads and terminals, resist pattern 92 is formed (FIG. 11C). Thereafter, by the use of electroplating, only on the exposed portion of the copper foil, a layer of gold plating 12 is formed on a under-layer of Ni (FIG. 11D).
Next, the portion corresponding, when adhered, to the position of the center-pads of a semiconductor chip is removed by die-cutting (FIG. 11E), thereafter, as a semiconductor package, the steps of assembling bonding wires 6, mounting solder balls 8 and others are carried out (FIG. 11F).
Incidentally, in such printed wired board 4 that is used in existing semiconductor package, as shown in FIG. 12, sandwiching an area corresponding to adhering position of a semiconductor chip that is shown by broken lines, extracting lines 19 for plating are disposed to supply electricity during electroplating. The extracting lines 19 for plating are connected electrically to terminals 20 for external input/output, bonding pads 21a and circuit pattern 22. Thus, the extracting lines 19 work as power supply lines during electroplating.
Then, in the step following the electroplating, portion A shown in FIG. 12 corresponding to the center-pad position of a semiconductor chip is removed by the use of die cutting. Further, the printed wired board 4, in a prescribed step of assembling as a semiconductor device, is finally cut along a dimension line conforming to a semiconductor chip. The external periphery portion is discarded as waste.
Accordingly, in the printed wired board for a conventional semiconductor package of chip scale size, since other than the area necessary as package, an area for extracting lines for plating is also necessary, thus a larger area necessary for fabrication is required. Accordingly, the number that is obtained with one sheet becomes small, causing a problem that the cost of the boards becomes expensive.
Further, the extracting lines for plating are formed straddling both inside and outside of the area of a semiconductor package. The extracting lines outside of the area, being unnecessary as the package, after the plating, are cut off. However, the portion inside of the package area remains within the board, thereby causing lowering of wiring efficiency. Further, when shrinkage of semiconductor packages or narrow ball pitch is forwarded, there is a problem that the area of wiring is squeezed further to result in incapability of drawing of circuit pattern.
That is, from terminals 20 for external input/output, circuit pattern 22 extending to bonding pads 21a is intrinsically necessary, at the same time, circuit pattern 22 extending to extracting lines 19 for plating is also necessary. Accordingly the amount of the circuit pattern from terminals 20 for external input/output increases.
The present invention was carried out to solve such problems. An object of the present invention is to provide a fabricating method of semiconductor devices in which on a functional surface of a semiconductor chip of center-pad structure a printed wired board is adhered, and center-pads of the semiconductor chip and bonding pads of the printed wired board are connected through bonding wires. In this fabricating method, an area for extracting lines for plating of the printed wired board can be made small and at the same time the number of the extracting lines for plating within a packaging area can be made small, resulting in an improvement of wiring efficiency. Thereby, even when shrinkage of semiconductor packages or narrow ball pitch is forwarded, the degree of freedom of drawing of circuit pattern in the printed wired board can be made large.
Further, another object of the present invention is to provide a fabricating method of printed wired boards which are adhered to a functional surface of semiconductor chips of center-pad structure and the bonding pads thereof are connected to the center-pads of the semiconductor chips through bonding wires. In this fabricating method, an area for extracting lines for plating of the printed wired boards is made small and at the same time the number of the extracting lines for plating within a package area is made small, resulting in an improvement of wiring efficiency. Thereby, even when the shrinkage of semiconductor packages or narrow ball pitch is forwarded, the degree of freedom of drawing of circuit pattern in the printed wired board can be made large.
Further, the present invention involves a printed wired board that is adhered to a functional surface of a semiconductor chip of center-pad structure and the bonding pads thereof are connected to the center-pads of the semiconductor chip through bonding wires. An object of the present invention is to provide a printed wired board in which an area for extracting lines for plating of the printed wired board is made small and at the same time the number of the extracting lines for plating within a packaging area is made small, resulting in an improvement of wiring efficiency. Accordingly even when the shrinkage of semiconductor packages or narrow ball pitch is forwarded, the degree of freedom of drawing of circuit pattern in the printed wired board can be made large.
The present invention relates to a fabricating method of semiconductor devices in which on a functional surface of a semiconductor chip of center-pad structure a printed wired board is adhered and center-pads of the semiconductor chip and bonding pads of the printed wired board are connected through bonding wires. Here, metallic foil of a laminate plate that is formed by laminating metallic foil and insulating film is etched. Thereby, in an area corresponding to center-pads of the semiconductor chip being adhered an extracting line for plating, in an area corresponding to the other portion than the above of the semiconductor chip terminal portions for external input/output and bonding pads, and straddling both the areas circuit pattern electrically connecting these are formed, respectively, to obtain a printed wired board. The present invention comprises the aforementioned steps of forming a printed wired board. The present invention further comprises the steps of implementing electroplating to the terminals for external input/output and the bonding pads while supplying electricity from the extracting line for plating of the printed wired board, removing an area of the printed wired board corresponding to the center-pads of the semiconductor chip together with the extracting line for plating to form a window, adhering the insulating film side of the printed wired board to the semiconductor chip so that the center-pads are exposed from the window, connecting the bonding pads of the printed wired board and the center-pads of the semiconductor chip with bonding wires, and forming terminals for external input/output at the terminal portions for external input/output of the printed wired board.
Further, here, the semiconductor chip may be one preceding dicing operation in which a lot of semiconductor chips are formed in matrix on a wafer.
In addition, here, the laminate plate may be one that is formed by laminating copper foil and polyimide based film. As the polyimide based film polyamide-imide film can be employed, and polyester film also can be employed. Lamination can be implemented by coating the filming material on the metallic foil instead of connecting metallic foil and insulating film with adhesive.
In addition, here, as to the copper foil, the thickness thereof may be set in the range of from 10 xcexcm to 20 xcexcm, and as to the polyimide based film, the thickness thereof may be set in the range of from 25 xcexcm to 75 xcexcm.
Still further, the width of the window may be in the range of from 0.5 mm to 2 mm.
A fabricating method of printed wired boards of the present invention comprises the steps of forming, by carrying out etching to metallic foil of a laminate plate obtained by laminating the metallic foil and insulating film, an extracting line for plating in an area corresponding to center-pads of a semiconductor chip being adhered, terminal portions for external input/output and bonding pads in an area corresponding to the other portion than the above of the semiconductor chip, and circuit pattern electrically connecting these while straddling both the areas, respectively, implementing electroplating, while supplying electricity from the extracting line for plating of the laminate plate, to the terminal portions for external input/output and the bonding pads, and removing an area of the laminate plate corresponding to the center-pads of the semiconductor chip together with the extracting line for plating to form a window portion.
Here, the laminate plate may be one formed by laminating copper foil and polyimide based film. As the polyimide based film polyamide-imide film can be employed, and polyester film also can be employed. Lamination can be implemented by coating the filming material on the metallic foil instead of connecting metallic foil and insulating film with adhesive.
In addition, here, as to the copper foil, the thickness thereof may be set in the range of from 10 xcexcm to 20 xcexcm, and as to the insulating film, the thickness thereof may be set in the range of from 25 xcexcm to 75 xcexcm.
Still further, the width of the window may be in the range of from 0.5 mm to 2 mm.
A printed wired board of the present invention comprises terminal portions for external input/output and bonding pads both of which are disposed on the other area than that corresponding to the center-pads of a semiconductor chip being adhered, and circuit pattern connecting these electrically. Here, the circuit pattern that is laid out from the terminal potions for external input/output is only that which reaches the bonding pads, and the bonding pads are ones that are electroplated by supplying electricity from the center-pad side of the semiconductor chip.
That is, the printed wired board, being electroplated by supplying electricity from the side of center-pad of the semiconductor chip, is not formed extracting line for plating directing towards the periphery thereof.
Further, as to the electroplating layer, on a seed layer of Ni of the thickness of from 2 xcexcm to 10 xcexcm, a Au layer of the thickness of from 0.1 xcexcm to 2 xcexcm may be used.
As to the circuit pattern, the thickness thereof may be set in the range of from 30 xcexcm to 150 xcexcm.
Further, as the bonding wire, Au may be employed.